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Recordings will be updated on the upcoming days - one by one
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Day-1 | Introduction to Embedded System
Day-2 | Introduction to VHDL and FPGA
Day - 3 | VHDL Datatypes and Operators
Day - 4 Operators and Datatypes
Day - 5 Modelling Styles
Day - 6 Testbenches
Day - 07 Ripple Carry Adder and FSM
Day - 08 Understanding K- Maps
Day 09 Practicing K -Maps
Day_10 Mealy Machine
Day11 Introduction to Memory
LIVE Recordings
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Day-1 | Introduction to Embedded System (137:57)
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Day-2 | Introduction to VHDL and FPGA (92:51)
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Day - 3 | VHDL Datatypes and Operators (90:41)
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Day - 4 Operators and Datatypes (78:09)
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Day - 5 Modelling Styles (92:43)
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Day - 6 Testbenches (89:13)
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Day - 07 Ripple Carry Adder and FSM (62:34)
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Day - 08 Understanding K- Maps (79:18)
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Day 9 Practicing K -Maps (69:39)
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Day 10 (58:28)
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Day11 Introduction to Memory (63:15)
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Day 12 (61:19)
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Day 13 Packages and Libraries (56:05)
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Advanced Techniques in VHDL (58:21)
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Interface LED & Switch with FPGA using VHDL (47:57)
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Interface LCD with FPGA using VHDL (72:36)
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Interface 7 Segment display with FPGA using VHDL (38:57)
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day 18 part 1 (88:18)
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Day 18_ part 2 (71:59)
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Day 19 (41:04)
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Day 20 - UART Interface (48:00)
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Day 21 - Part 1 (64:24)
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Day 21 - Part 2 (65:15)
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Day 22 - Temperature UART (56:12)
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Day 23 - Ultrasonic Sensor Interface (42:28)
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Day 24 - WIFI Interfacing (56:30)
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Day 24 - WIFI Interfacing Part 2 (39:52)
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Day 25 - (28:41)
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Day 26 - 4 Bit Sum Series Architecture (35:42)
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Day 27 MIPS Architecture (50:52)
