Signals and Variables | Pantech University

Autoplay
Autocomplete

Previous Lesson Complete and Continue

Internship on FPGA using VHDL

Mandatory Step First Step - Join the Community Here

Join VIP Telegram Group
Join Private Community

Recordings will be updated on the upcoming days - one by one

Recordings will be updated on the upcoming days - one by one

Download Your Course Repository

Download Now

Day-1 | Introduction to Embedded System

Introduction & Explanation (69:06)

Day-2 | Introduction to VHDL and FPGA

INTRODUCTION TO VLSI (12:10)
VLSI DESIGN FLOW (6:43)
HARDWARE DESCRIPTION LANGUAGE (2:06)
VHDL (2:50)
FPGA AND ITS ARCHITECTURE (15:39)
LOOK UP TABLES CONTINUED (4:04)
ABSTRACTION (9:41)

Day - 3 | VHDL Datatypes and Operators

Structure of a Basic VHDL Code (10:42)
Library and Entity Declaration (6:05)
Architecture Declaration (5:28)
The Process (8:36)
Wait Statement (8:08)

Day - 4 Operators and Datatypes

Pre-Defined Data types (11:49)
Signals and Variables (8:05)
Legal Operations (4:50)
Operators (15:20)

Day - 5 Modelling Styles

Modelling Styles in VHDL (1:37)
Structural Modelling (3:18)
Navigating through VIVADO (4:40)
XOR Gate in VHDL (7:29)
AND GATE in VHDL (4:40)
Half Adder using structural modelling (12:15)
Half Adder using Behavioral modelling (8:53)
Half Adder using Dataflow modelling (4:02)
Full Adder Task (2:41)

Day - 6 Testbenches

An important note to learning (1:12)
The full adder, sub heading : a brief idea on writing the code (3:08)
Ripple Carry Adder (12:19)
Test Benches (5:51)
Writing a test bench (14:13)
Configuration Package (13:25)
Running and analyzing the simulation (4:14)

Day - 07 Ripple Carry Adder and FSM

Full Adder Structural, on VHDL (19:39)
Ripple Carry Adder Structural, on VHDL (14:29)
Test Bench for Ripple Carry Adder and simulation (11:33)
Finite State Machine (15:46)

Day - 08 Understanding K- Maps

Types of FSMs (10:52)
K- Maps, Two Variable (22:31)
Three Variable K- Map (17:35)
Four Variable K- Map (22:51)

Day 09 Practicing K -Maps

K -Maps Practice (19:26)
Don't Care Condition (10:32)
Drawing a Finite state Diagram (14:08)
State Truth Table (13:36)
Drawing a Finite state Diagram (6:34)
FSM logic circuit (3:33)

Day_10 Mealy Machine

Review of previous lesson (3:38)
Mealy Machine state diagram (8:35)
State truth table and Circuit diagram (18:02)
Behavioral FSMs in VHDL (26:12)

Day11 Introduction to Memory

Objective and Intro to Memory (5:36)
Capturing Data (8:31)
Latches (15:11)
D latch (12:59)
FlipFlops (7:27)
D Flip Flops and Registers (4:09)
Memory Mapping (7:14)

LIVE Recordings

Day 12 (61:19)
Day 13 Packages and Libraries (56:05)
Advanced Techniques in VHDL (58:21)
Interface LED & Switch with FPGA using VHDL (47:57)
Interface LCD with FPGA using VHDL (72:36)
Interface 7 Segment display with FPGA using VHDL (38:57)
day 18 part 1 (88:18)
Day 18_ part 2 (71:59)
Day 19 (41:04)
Day 20 - UART Interface (48:00)
Day 21 - Part 1 (64:24)
Day 21 - Part 2 (65:15)
Day 22 - Temperature UART (56:12)
Day 23 - Ultrasonic Sensor Interface (42:28)
Day 24 - WIFI Interfacing (56:30)
Day 24 - WIFI Interfacing Part 2 (39:52)
Day 25 - (28:41)
Day 26 - 4 Bit Sum Series Architecture (35:42)
Day 27 MIPS Architecture (50:52)

Teach online with

Signals and Variables

Lesson content locked

If you're already enrolled, you'll need to login.

Enroll in Course to Unlock