Mandatory Step First Step - Join the Community Here
Recordings will be updated on the upcoming days - one by one
Download Your Course Repository
Day-1 | Introduction to Embedded System
Day-2 | Introduction to VHDL and FPGA
Day - 3 | VHDL Datatypes and Operators
Day - 4 Operators and Datatypes
Day - 5 Modelling Styles
Day - 6 Testbenches
Day - 07 Ripple Carry Adder and FSM
Day - 08 Understanding K- Maps
Day 09 Practicing K -Maps
Day_10 Mealy Machine
Day11 Introduction to Memory
LIVE Recordings
-
Day 12 (61:19)
-
Day 13 Packages and Libraries (56:05)
-
Advanced Techniques in VHDL (58:21)
-
Interface LED & Switch with FPGA using VHDL (47:57)
-
Interface LCD with FPGA using VHDL (72:36)
-
Interface 7 Segment display with FPGA using VHDL (38:57)
-
day 18 part 1 (88:18)
-
Day 18_ part 2 (71:59)
-
Day 19 (41:04)
-
Day 20 - UART Interface (48:00)
-
Day 21 - Part 1 (64:24)
-
Day 21 - Part 2 (65:15)
-
Day 22 - Temperature UART (56:12)
-
Day 23 - Ultrasonic Sensor Interface (42:28)
-
Day 24 - WIFI Interfacing (56:30)
-
Day 24 - WIFI Interfacing Part 2 (39:52)
-
Day 25 - (28:41)
-
Day 26 - 4 Bit Sum Series Architecture (35:42)
-
Day 27 MIPS Architecture (50:52)
